1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a memory device compatible with synchronous static random access memory devices, which employs dynamic random access memory cells.
2. Description of the Related Art
Generally, random access memory (RAM) devices are classified into static RAM (SRAM) devices and dynamic RAM (DRAM) devices. A RAM device generally includes a memory array composed of a plurality of unit memory cells arranged in a matrix form defined by rows and columns, and peripheral circuits adapted to control the input/output of data to/from the unit memory cells. Each of the unit memory cells stores one bit of data. In an SRAM, each unit memory cell is implemented using four transistors that form a latch structure and two transistors that act as transmission gates. Since SRAM devices store data in unit memory cells having latch structures, no refresh operation is required to maintain the stored data. Further, the SRAM devices have the advantages of a fast operating speed and low power consumption compared to DRAM devices.
However, since each unit memory cell of an SRAM is composed of six transistors, the SRAM is disadvantageous in that it requires a large wafer area compared to a DRAM that generally has unit memory cells each implemented using a transistor and a capacitor. In more detail, in order to manufacture a semiconductor memory device of the same capacity, the SRAM requires a wafer about six to ten times larger than that of the DRAM. The necessity of such a large wafer increases the unit cost of the SRAM. When a DRAM instead of an SRAM is used to reduce the cost, a DRAM controller is additionally required to perform a periodic refresh operation. Further, the entire performance of a system is deteriorated due to the time required to perform the refresh operation and a slow operating speed.
In order to overcome the disadvantages of the DRAM and the SRAM, attempts have been made to implement an SRAM to which DRAM memory cells are applied. One of these attempts is the technology of effectively concealing a refresh operation from the outside of the memory to enable the memory to be compatible with the SRAM.
In the conventional SRAM-compatible technology, an additional time period is required for internal refresh operation within a memory access interval or memory access timing is delayed in order to obtain a time required to refresh DRAM cells of a memory array.
However, such a conventional synchronous SRAM-compatible memory is problematic in that the memory access timing for writing/reading is internally delayed, and an overall operating speed is decreased due to the delay of the access timing.
The above-discussed and other problems and deficiencies occurring in the prior art are overcome or alleviated by a synchronous SRAM-compatible memory of the present invention, which is compatible with SRAM even while exploiting DRAM memory cells, synchronizes with an external clock signal, and minimizes a decrease in operating speed due to a refresh operation.
The present invention provides a synchronous SRAM-compatible memory having a DRAM memory array including a plurality of DRAM cells arranged in a matrix form defined by rows and columns, operating in synchronization with a reference clock signal, and interfacing with an external system that simultaneously provides a row address for selecting a row of the DRAM memory array and a column address for selecting a column thereof, where the DRAM cells require a refresh operation at regular refresh periods to maintain data stored therein. The synchronous SRAM-compatible memory includes a DRAM memory array; a data input/output unit for controlling input and output of data to and from the DRAM memory array; a state control unit for controlling an operation of accessing the DRAM memory array and an operation of the data input/output unit, the state control unit receiving a chip enable signal externally provided to enable the synchronous SRAM/compatible memory device; a refresh timer for generating a refresh request signal activated at regular intervals; a clock period modulating unit for providing a pre-control signal to activate a non-executed refresh request signal, the pre-control signal being designed so that a logic state thereof transitions in response to every n-th reference clock signal generated during an inactivation interval of the chip enable signal; and a refresh control unit for generating a refresh control signal to be activated to control a refresh operation to be performed for the DRAM memory array, the refresh control signal being activated in response to transition of the pre-control signal.
The refresh control signal is activated in response to a refresh clock signal having a period xe2x80x9cnxe2x80x9d (n is a natural number) times a period of the reference clock signal. The period of the refresh clock signal may be 1/m (m is a natural number) of an inactivation interval of the chip enable signal.